This invention relates to a digital CCD (charge coupled device) arrangement of the type which includes a semiconductor layer of the first conductivity type, a row of shift electrodes arranged in insulated fashion above said semiconductor layer, which electrodes are fed with pulse train voltages displaced in phase relative to one another. The arrangement further includes an output end zone of a conductivity type opposite to that of said semiconductor layer, which is connected on the one hand to a switch which intermittently supplies a first reference potential and, on the other hand, to the input of a transistor stage.
Arrangements of this kind are described in the publication by Kosonocky "Charge-Coupled Device--An Overview" in the Wescon Technical Papers, Vol. 18, September 1974, No. 2/1, pages 1 to 20, wherein the consecutive logic states of a digital input signal are consecutively evaluated in that the one logic state (e.g., "1") leads to an accumulation of charge carriers in a potential well beneath the first shift electrode, whereas the other logic state, e.g., "0", does not. Since, between the individual evaluation processes, the previously formed charge carriers are shifted by a predetermined number of electrode intervals, the digital input signal is converted into a sequence of charge carrier parcels and displaced in this form in the semiconductor layer along the row of electrodes in the direction towards the output-end zone of opposite conductivity type in stepped fashion. The output-end field effect transistor stage which is illustrated in FIG. 10(b) of this publication and which initially emits a first logic signal level of a digital output signal, is caused to emit a second logic signal level when the individual charge carrier parcels penetrate into the output end zone so that a digital output signal is formed which corresponds to the input signal and normally is inverted. Due to the so-called dark current which arises from thermally generated charge carriers, however, in addition undesired charge carriers are accumulated beneath the electrodes and adulterate the described process. A further fault influence consists in that not all the charge carriers are transported from one shift electrode to the next. Due to these adverse influences, the voltage range of the output signal can be reduced to such an extent that in many cases it is no longer adequate to ensure fault-free signal transmission.
So-called regenerator circuits are now employed, the function of which is to re-establish the full voltage range between the logic signal states of the output signal.
In the integrated MOS circuit technique, for the purpose of regeneration, for example, in addition to a first CCD arrangement, on the same substrate there is provided a similar, second arrangement which is operated with the same pulse train voltages (see IEEE Journal of Solid-State Circuits, Vol. SC-7, 1972, pages 237-242, in particular FIG. 3), wherein, in the semiconductor layer of the first arrangement beneath one of the shift electrodes there is provided an oppositely doped semiconductor zone which is connected to a shift electrode of the second arrangement which serves as input electrode for that part of this arrangement which lies at its output end. The charge carriers of the first arrangement which represent the binary input signal then control the potential of the shift electrode which is employed as input electrode, the signal analysis taking place at the output of the second arrangement. However, fault-free signal transmission is conditional upon the shift electrode which serves as input electrode being provided with a sufficient potential difference during the sampling of the charges which have been shifted in the first arrangement.
The IEEE Journal of Solid-State Circuits, Vol. SC-11, 1976, No. 1, pages 18-24, in particular FIG. 8, relates to a CCD arrangement of the type described above, having a regenerating logic in MOS technology which contains a flip-flop. This flip-flop is fed on the one hand with the potential of the output-end zone of opposite conductivity and on the other hand with a reference voltage which is formed in a further CCD arrangement comprising a following comparator circuit, in that said reference voltage lies between the potentials of the output-end zone during the evaluation of the logic states "0" and "1". Then, in dependence upon the overshooting or undershooting of a reference voltage by the potential of the output-end zone, a digital signal exhibiting a satisfactory voltage range is emitted from the outputs of the flip-flop. The circuitry outlay required for this purpose is considerable however. In this known arrangement, the output-end zone of opposite conductivity is additionally preceded by an electrode which is insulated from the semiconductor layer and which is connected to a predetermined, further reference potential which serves as potential barrier.